Titan: Difference between revisions
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The '''Titan''' is a development board used during [[Bringup]] of the [[Shiva (CPU)|Shiva]] and [[Waternoose (CPU) | The '''Titan''' is a development board used during [[Bringup]] of the [[Shiva (CPU)|Shiva]] and [[Waternoose (CPU)|Waternoose]] Engineering Sample CPUs. It also allows an IBM RISCWatch to be used to debug and test the processors. | ||
== Specifications == | == Specifications == | ||
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The 10-pin J_YETI header connects to J8C1, the CPU JTAG header, while the 12-pin J_GPUL header connects to J7G2, the [[Shiva]] JTAG header. | The 10-pin J_YETI header connects to J8C1, the CPU JTAG header, while the 12-pin J_GPUL header connects to J7G2, the [[Shiva]] JTAG header. | ||
Different bitstreams are required for [[Shiva]], and various revisions of [[Waternoose (CPU)|Waternoose]]. | |||
== Gallery == | == Gallery == | ||
Revision as of 15:32, 3 January 2023
 Titan II | |
| Designed By | IBM |
|---|---|
The Titan is a development board used during Bringup of the Shiva and Waternoose Engineering Sample CPUs. It also allows an IBM RISCWatch to be used to debug and test the processors.
Specifications
- Xilinx Spartan 3 XC3S200 FPGA
- 128KB Xilinx XCF01S JTAG PROM
- 4 DIP Switches
- 9 3.3V LEDs (Later versions only)
- 50MHz 3.3V Crystal
Details
The Titan is powered off the console via the 3.3V V_MEMPORT and 1.8V V_1P8 rails. The 3.3V is also stepped down to 2.5V and 1.2V.
The 10-pin J_YETI header connects to J8C1, the CPU JTAG header, while the 12-pin J_GPUL header connects to J7G2, the Shiva JTAG header.
Different bitstreams are required for Shiva, and various revisions of Waternoose.
Gallery
XeDK 007 with Titan II powered on
