XCPU: Difference between revisions

From XenonLibrary
Jump to navigation Jump to search
No edit summary
 
(51 intermediate revisions by the same user not shown)
Line 1: Line 1:
{{Infobox Chip
{{Infobox Chip
| name        = XCPU
| name        = XCPU
| introduced  = 2005
| image        = X02046-003.jpg
| image_size  = 150px
| caption      = The original XCPU, [[Waternoose]]
| introduced  = Late 2005
| designedby  = IBM<br>Microsoft
| codename    = Xenon
| codename    = Xenon
| type        = CPU
| type        = CPU
| usedin      = [[Xbox 360]]
| usedin      = [[Original Xbox 360]]
| clockspeed  = 3.2GHz
| clockspeed  = 3.2GHz
| cache        = L1: 32KB/32KB<br>L2: 1MB
| cache        = L1: 32KB/32KB<br>L2: 1MB
Line 10: Line 14:
| cores        = 3
| cores        = 3
| threads      = 6
| threads      = 6
| predecessor  = [[Shiva]]
| successor    = [[XCGPU]]
}}
}}
{{See also|GPU|XCGPU}}


The '''Microsoft XCPU''', codenamed '''Xenon''', is the central processor used in the [[Xbox 360]] game console. It is designed to be used with the ATi [[Xenos]] graphics chip, which also functions as the northbridge and memory controller.
The '''Microsoft XCPU''', codename '''Xenon''', is the central processor used in the [[Xbox 360]]. It is designed to be used with the ATi [[Xenos]] graphics chip, which also functions as the northbridge and memory controller.


The processor was developed by Microsoft and IBM, and the first version was codenamed [[Waternoose (CPU)|Waternoose]] after the fictional character [https://en.wikipedia.org/wiki/List_of_Monsters,_Inc._characters#Henry_J._Waternoose_III Henry J. Waternoose III].
The processor was developed by Microsoft and IBM, and the first version was codenamed [[Waternoose]] after the fictional character [https://en.wikipedia.org/wiki/List_of_Monsters,_Inc._characters#Henry_J._Waternoose_III Henry J. Waternoose III].
 
Waternoose is the first "real" CPU for the Xbox 360, replacing the earlier [[Shiva]] CPU, which was only used for early development.


== Specifications ==
== Specifications ==
* 3 two-way SMD-capable RISC cores clocked at 3.2GHz
{{CPU Specs}}
* SIMD: Two VMX128 units
 
* 32KB L1 data cache
=== Secure ROM ===
* 32KB L1 instruction cache
All version of the XCPU contain a One-Time-Programmable (OTP) Secure ROM using [[eFUSEs]]. This ensures that it can never be modified after being written. The Secure ROM contains the [[1BL]], [[config ring]], and [[configuration fuses]].
* 1MB L2 cache at 1.6 GHz with a 256-bit bus
* 21.6GB/s [[FSB]]
* 768 bits of IBM [[eFUSE]] one-time-program memory
* ROM and 64KB SRAM for storing the [[1BL]]
* Big-endian architecture


== Versions ==
=== SRAM ===
Multiple versions of the XCPU have been created for different motherboard types
The cache in the XCPU is used as SRAM for the [[1BL]] and [[2BL]] bootloaders, as [[system RAM]] is not yet available.


=== 90nm ===
== Variants ==
{{Main|Waternoose (CPU)}}


The initial version of the XCPU, codename '''Waternooose''', entered production in 2005 and is used on the [[Xenon (Motherboard)|Xenon]] and [[Zephyr]] motherboards. It is notable for running hot and being power hungry.
=== Waternoose (90nm) ===
{{Main|Waternoose}}


=== 65nm ===
The initial versions of the XCPU, known as [[Waternoose]], entered production in 2005 and are used on the [[Xenon (Motherboard)|Xenon]] and [[Zephyr]] motherboards. It is notable for being quite power hungry.
{{Main|Loki (CPU)}}


In 2007, the XCPU was shrunk and slightly redesigned for the 65nm process. Codename '''Loki''', it is used on the [[Falcon]] and [[Jasper]] motherboards. It is notable for running cool and having a significantly lower TDP.
=== Loki (65nm) ===
{{Main|Loki}}


=== 45nm (CGPU) ===
In 2007, the XCPU was shrunk and slightly redesigned for the 65nm process. Named [[Loki]], it is used on the [[Falcon]] and [[Jasper]] motherboards. It is notable for having significantly lower power and thermal requirements.
{{Main|Valhalla (CGPU)}}


In 2010, the XCPU was shrunk to the 45nm process and combined with the [[Xenos]] graphics chip to create a system-on-a-chip, called the [[XCGPU]]. The [[eDRAM]] remains on a separate die and an [[IHS]] was added. Codename '''Valhalla''', it is used on the [[Trinity]] and [[Corona]] motherboards.
=== XCGPU ===
{{Main|XCGPU}}


=== Winchester ===
In 2010, the XCPU was combined with the GPU to create a system-on-a-chip, called the [[XCGPU]].
{{Main|Winchester CGPU}}


In 2014, the XCGPU process was shrunk by an unknown amount and the eDRAM die was integrated into the CGPU die. The codename and specifics for this chip are unknown. The single die design meant that the [[IHS]] was no longer needed. It is used on the [[Winchester]] motherboard and is notable for patching the RGH exploit.
{{Motherboard Components}}
[[Category:Motherboard Components]]

Latest revision as of 16:24, 5 April 2024

XCPU
X02046-003.jpg
The original XCPU, Waternoose
IntroducedLate 2005
Designed ByIBM
Microsoft
CodenameXenon
TypeCPU
Used InOriginal Xbox 360
Clock Speed3.2GHz
CacheL1: 32KB/32KB
L2: 1MB
Instruction SetPowerPC RISC
Cores3
Threads6
PredecessorShiva
SuccessorXCGPU
See also: GPU and XCGPU

The Microsoft XCPU, codename Xenon, is the central processor used in the Xbox 360. It is designed to be used with the ATi Xenos graphics chip, which also functions as the northbridge and memory controller.

The processor was developed by Microsoft and IBM, and the first version was codenamed Waternoose after the fictional character Henry J. Waternoose III.

Waternoose is the first "real" CPU for the Xbox 360, replacing the earlier Shiva CPU, which was only used for early development.

Specifications

  • 3 two-way SMD-capable RISC cores clocked at 3.2GHz
  • SIMD: Two VMX128 units
  • 32KB L1 data cache
  • 32KB L1 instruction cache
  • 1MB L2 cache at 1.6 GHz with a 256-bit bus
  • 21.6GB/s FSB
  • 768 bits of IBM eFUSE One-Time-Program memory for fusesets
  • One-Time-Programmable ROM and 64KB SRAM for the 1BL and Config Ring
  • Big-endian architecture

Secure ROM

All version of the XCPU contain a One-Time-Programmable (OTP) Secure ROM using eFUSEs. This ensures that it can never be modified after being written. The Secure ROM contains the 1BL, config ring, and configuration fuses.

SRAM

The cache in the XCPU is used as SRAM for the 1BL and 2BL bootloaders, as system RAM is not yet available.

Variants

Waternoose (90nm)

Main article: Waternoose

The initial versions of the XCPU, known as Waternoose, entered production in 2005 and are used on the Xenon and Zephyr motherboards. It is notable for being quite power hungry.

Loki (65nm)

Main article: Loki

In 2007, the XCPU was shrunk and slightly redesigned for the 65nm process. Named Loki, it is used on the Falcon and Jasper motherboards. It is notable for having significantly lower power and thermal requirements.

XCGPU

Main article: XCGPU

In 2010, the XCPU was combined with the GPU to create a system-on-a-chip, called the XCGPU.

Retrieved from "https://xenonlibrary.com/index.php?title=XCPU&oldid=3437"