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* Purpose: [[CGPU]] [[PCIe]] Power * Purpose: [[Southbridge]] [[PCIe]] Power

* Purpose: [[GPU]] [[PCIe]] Power * Purpose: [[Southbridge]] [[PCIe]] Power

* 4x 100MHz differential: CPU, GPU, PCIe, SATA

''' Set FSB/PCIe/Memory Calibration ''' * PCIe:

...ly known change from [[Rhea]] to create Elpis was swizzling (flipping) the PCIe balls on the chip in order to match the ballout of the original 90nm [[Y1 (

The PCIe ballout was de-swizzled (flipped) for the [[Zephyr#Zephyr_B|Zephyr_B]] moth

* The [[PCIe]] pads under the GPU have been de-swizzled in order to support the Y2 GPU

..._RST_DONE during [[SMC#seqUnReset|seqUnReset]], the [[SMC]] monitors the [[PCIe]] L0 status and waits for the link to enter the L0 state. If the link does | 0021 || 0x09 || ERROR_NO_PCIE || PCIe link did not enter L0 after seqUnReset time passed || EC_BOOT || Bad GPU ||