Post Codes: Difference between revisions
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Revision as of 21:26, 17 June 2023
The Xbox 360 uses Post Codes to report the current step of the boot process. They can be read using 8 post points on the bottom of the motherboard which form a hex byte.
Post Codes List
The "Possible Cause" indicates possible reasons for post code if the unit is displaying an error code on the front panel or hanging on boot.
1BL
Not applicable to Waternoose DD1, Shiva, or when Secure ROM is not used.
Hex | Name | Description | Possible Cause |
---|---|---|---|
0x10 | BEGIN | 1BL entry point | |
0x11 | FSB_CONFIG_PHY_CONTROL | FSB function 1 | FSB fail |
0x12 | FSB_CONFIG_RX_STATE | FSB function 2 | FSB fail |
0x13 | FSB_CONFIG_TX_STATE | FSB function 3 | FSB fail |
0x14 | FSB_CONFIG_TX_CREDITS | FSB function 4 | FSB fail |
0x15 | FETCH_OFFSET | Fetch 2BL offset in flash | GPU, SB, Nand |
0x16 | FETCH_HEADER | Fetch 2BL header from flash | |
0x17 | VERIFY_HEADER | Verify 2BL header | Bad 2BL header |
0x18 | FETCH_CONTENTS | Copy 2BL to SRAM | Bad nand image |
0x19 | HMACSHA_COMPUTE | Compute 2BL HMAC hash | |
0x1A | RC4_INITIALIZE | Initialize 2BL RC4 | |
0x1B | RC4_DECRYPT | Decrypt 2BL | Bad nand image |
0x1C | SHA_COMPUTE | Compute 2BL hash | |
0x1D | SIG_VERIFY | Verify 2BL hash | Bad 2BL signature |
0x1E | BRANCH | Branch to 2BL |
2BL
Later retail systems uses a split 2BL which added the CB_A and renamed the CB to CB_B. Earlier units and developer systems use a single 2BL.
CB_A
Hex | Name | Description | Possible Cause |
---|---|---|---|
0xD0 | CB_A entry point | ||
0xD1 | READ_FUSES | Read eFUSEs | |
0xD2 | VERIFY_OFFSET_CB_B | Verify CB_B offset in flash | Bad nand image |
0xD3 | FETCH_HEADER_CB_B | Fetch CB_B header from flash | |
0xD4 | VERIFY_HEADER_CB_B | Verify CB_B header | Bad CB_B header |
0xD5 | FETCH_CONTENTS_CB_B | Copy CB_B to SRAM | Bad nand image |
0xD6 | HMACSHA_COMPUTE_CB_B | Generate CB_B hash | |
0xD7 | RC4_INTIALIZE_CB_B | Initialize CB_B RC4 | |
0xD8 | RC4_DECRYPT_CB_B | Decrypt CB_B | Bad nand image |
0xD9 | SHA_COMPUTE_CB_B | Compute CB_B hash | |
0xDA | SHA_VERIFY_CB_B | Verify CB_B hash | Bad CB_B signature |
0xDB | BRANCH_CB_B | Branch to CB_B |
CB/SB/CB_B
Hex | Name | Description | Possible Cause |
---|---|---|---|
0x20 | 2BL entry point, initialize SoC | ||
0x21 | INIT_SECOTP | Initialize Secure ROM and eFUSEs | |
0x22 | INIT_SECENG | Initialize security engine | |
0x23 | INIT_SYSRAM | Initialize system RAM | Bad GPU, RAM |
0x24 | VERIFY_OFFSET_3BL | Verify 3BL offset in flash | Bad nand image |
0x25 | LOCATE_3BL | Locate 3BL in flash | Bad nand image |
0x26 | FETCH_HEADER_3BL | Fetch 3BL header from flash | |
0x27 | VERIFY_HEADER_3BL | Verify 3BL header | Bad 3BL header |
0x28 | FETCH_CONTENTS | Copy 3BL to SRAM | Bad nand image |
0x29 | HMACSHA_COMPUTE_3BL | Generate 3BL hash | |
0x2A | RC4_INITIALIZE_3BL | Initialize 3BL RC4 | |
0x2B | RC4_DECRYPT_3BL | Decrypt 3BL | Bad nand image |
0x2C | SHA_COMPUTE_3BL | Compute 3BL hash | |
0x2D | SHA_VERIFY_3BL | Verify 3BL hash | Bad 3BL signature |
0x2E | HWINIT | Hardware initialization | Bad GPU, RAM |
0x2F | RELOCATE | Relocate to system RAM | |
0x30 | VERIFY_OFFSET_4BL | Verify 4BL offset in flash | Bad nand image |
0x31 | FETCH_HEADER_4BL | Fetch 4BL header from flash | |
0x32 | VERIFY_HEADER_4BL | Verify 4BL header | Bad 4BL header |
0x33 | FETCH_CONTENTS_4BL | Copy 4BL to RAM | Bad nand image |
0x34 | HMACSHA_COMPUTE_4BL | Generate 4BL hash | |
0x35 | RC4_INITIALIZE_4BL | Initialize 4BL RC4 | |
0x36 | RC4_DECRYPT_4BL | Decrypt 4BL | Bad nand image |
0x37 | SHA_COMPUTE_4BL | Compute 4BL hash | |
0x38 | SIG_VERIFY_4BL | Verify 4BL hash | Bad 4BL signature |
0x39 | SHA_VERIFY_4BL | Verify 4BL hash | Bad 4BL signature |
0x3A | BRANCH | Branch to 4BL | |
0x3B | PCI_INIT | Initialize PCI |
1BL Panics
Hex | Name | Description | Possible Cause |
---|---|---|---|
0x81 | MACHINECHECK | Panic - Machine Check | |
0x82 | DATA_STORAGE | Panic - Data Storage | |
0x83 | DATA_SEGMENT | Panic - Data Segment | |
0x84 | INSTRUCTION_STORAGE | Panic - Instruction Storage | |
0x85 | INSTRUCTION_SEGMENT | Panic - Instruction Segment | |
0x86 | EXTERNAL | Panic - External | CPU interrupt triggered |
0x87 | ALIGNMENT | Panic - Alignment | |
0x88 | PROGRAM | Panic - Program | Illegal instruction |
0x89 | FPU_UNAVAILABLE | Panic - FPU Unavailable | |
0x8A | DECREMENTER | Panic - Decrementer | |
0x8B | HYPERVISOR_DECREMENTER | Panic - Hypervisor Decrementer | |
0x8C | SYSTEM_CALL | Panic - System Call | |
0x8D | TRACE | Panic - Trace | |
0x8E | VPU_UNAVAILABLE | Panic - VPU Unavailable | |
0x8F | MAINTENANCE | Panic - Maintenance | |
0x90 | VMX_ASSIST | Panic - VMX Assist | |
0x91 | THERMAL_MANAGEMENT | Panic - Thermal Management | |
0x92 | WRONG_THREAD | Panic - Wrong Thread | 1BL executed on wrong thread |
0x93 | TOO_MANY_CORES | Panic - Too Many Cores | 1BL executer on wrong core |
0x94 | VERIFY_OFFSET | Panic - Verify Offset | Bad 2BL offset |
0x95 | VERIFY_HEADER | Panic - Verify Header | Bad 2BL header |
0x96 | SIG_VERIFY | Panic - Signature Verify | Bad 2BL signature |
0x97 | NONHOST_RESUME_STATUS | Panic - Non Host Resume Status | |
0x98 | NEXT_STAGE_SIZE | Panic - Next Stage Size | 2BL size too large |
2BL
Later retail systems uses a split 2BL which added the CB_A and renamed the CB to CB_B. Earlier units and developer systems use a single 2BL.
CB_A
Hex | Name | Description | Possible Cause |
---|---|---|---|
0xF0 | VERIFY_OFFSET_CB_B | Panic - Verify Offset | Bad CB_B offset |
0xF1 | VERIFY_HEADER_CB_B | Panic - Verify Header | Bad CB_B header |
0xF2 | SHA_VERIFY_CB_B | Panic - Signature Verify | Bad CB_B signature |
0xF3 | ENTRY_SIZE_INVALID_CB_B | Panic - Entry Size Invalid | CB_B size too large |
CB/SB/CB_B