Post Codes: Difference between revisions

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| 0x14 || FSB_CONFIG_TX_CREDITS || FSB function 4 || FSB fail
| 0x14 || FSB_CONFIG_TX_CREDITS || FSB function 4 || FSB fail
|-
|-
| 0x15 || FETCH_OFFSET || Fetch 2BL offset from flash || GPU, SB, Nand
| 0x15 || FETCH_OFFSET || Fetch 2BL offset in flash || GPU, SB, Nand
|-
|-
| 0x16 || FETCH_HEADER || Fetch 2BL header from flash || Bad 2BL header
| 0x16 || FETCH_HEADER || Fetch 2BL header from flash ||  
|-
|-
| 0x17 || VERIFY_HEADER || Verify 2BL header || Bad 2BL header
| 0x17 || VERIFY_HEADER || Verify 2BL header || Bad 2BL header
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| 0x1C || SHA_COMPUTE|| Generate 2BL hash ||  
| 0x1C || SHA_COMPUTE|| Generate 2BL hash ||  
|-
|-
| 0x1D || SIG_VERIFY || Verify 2BL hash with RSA || Bad 2BL signature
| 0x1D || SIG_VERIFY || Verify 2BL hash || Bad 2BL signature
|-
|-
| 0x1E || BRANCH || Branch to 2BL ||  
| 0x1E || BRANCH || Branch to 2BL ||  
|}
|}
=== 2BL ===
Later [[retail]] systems uses a [[split 2BL]] which added the CB_A and renamed the CB to CB_B. Earlier units and [[developer]] systems use a single 2BL.
==== CB_A ====
{|class="wikitable"
! Hex !! Name !! Description !! Possible Cause
|-
| 0xD0 || BEGIN || CB_A entry point ||
|-
| 0xD1 || READ_FUSES || Read eFUSEs ||
|-
| 0xD2 || VERIFY_OFFSET_CB_B || Verify CB_B offset in flash || Bad nand image
|-
| 0xD3 || FETCH_HEADER_CB_B || Fetch CB_B header from flash ||
|-
| 0xD4 || VERIFY_HEADER_CB_B || Verify CB_B header || Bad CB_B header
|-
| 0xD5 || FETCH_CONTENTS_CB_B || Copy CB_B to SRAM || Bad nand image
|-
| 0xD6 || HMACSHA_COMPUTE_CB_B || Generate CB_B hash ||
|-
| 0xD7 || RC4_INTIALIZE_CB_B || Initialize CB_B RC4 decryption key ||
|-
| 0xD8 || RC4_DECRYPT_CB_B || Decrypt CB_B with RC4 || Bad nand image
|-
| 0xD9 || SHA_COMPUTE_CB_B || Generate CB_B hash ||
|-
| 0xDA || SHA_VERIFY_CB_B || Verify CB_B hash || Bad CB_B signature
|-
| 0xDB || BRANCH_CB_B || Branch to CB_B ||
|}
==== CB/CB_B/SB ====
----


=== 1BL Panics ===
=== 1BL Panics ===

Revision as of 21:00, 17 June 2023

The Xbox 360 uses Post Codes to report the current step of the boot process. They can be read using 8 post points on the bottom of the motherboard which form a hex byte.

Post Codes List

The "Possible Cause" indicates possible reasons for post code if the unit is displaying an error code on the front panel or hanging on boot.

1BL

Not applicable to Waternoose DD1, Shiva, or when Secure ROM is not used.

Hex Name Description Possible Cause
0x10 BEGIN 1BL entry point
0x11 FSB_CONFIG_PHY_CONTROL FSB function 1 FSB fail
0x12 FSB_CONFIG_RX_STATE FSB function 2 FSB fail
0x13 FSB_CONFIG_TX_STATE FSB function 3 FSB fail
0x14 FSB_CONFIG_TX_CREDITS FSB function 4 FSB fail
0x15 FETCH_OFFSET Fetch 2BL offset in flash GPU, SB, Nand
0x16 FETCH_HEADER Fetch 2BL header from flash
0x17 VERIFY_HEADER Verify 2BL header Bad 2BL header
0x18 FETCH_CONTENTS Copy 2BL to SRAM Bad nand image
0x19 HMACSHA_COMPUTE Generate 2BL hash
0x1A RC4_INITIALIZE Initialize 2BL RC4 decryption key
0x1B RC4_DECRYPT Decrypt 2BL with RC4 Bad nand image
0x1C SHA_COMPUTE Generate 2BL hash
0x1D SIG_VERIFY Verify 2BL hash Bad 2BL signature
0x1E BRANCH Branch to 2BL

2BL

Later retail systems uses a split 2BL which added the CB_A and renamed the CB to CB_B. Earlier units and developer systems use a single 2BL.

CB_A

Hex Name Description Possible Cause
0xD0 BEGIN CB_A entry point
0xD1 READ_FUSES Read eFUSEs
0xD2 VERIFY_OFFSET_CB_B Verify CB_B offset in flash Bad nand image
0xD3 FETCH_HEADER_CB_B Fetch CB_B header from flash
0xD4 VERIFY_HEADER_CB_B Verify CB_B header Bad CB_B header
0xD5 FETCH_CONTENTS_CB_B Copy CB_B to SRAM Bad nand image
0xD6 HMACSHA_COMPUTE_CB_B Generate CB_B hash
0xD7 RC4_INTIALIZE_CB_B Initialize CB_B RC4 decryption key
0xD8 RC4_DECRYPT_CB_B Decrypt CB_B with RC4 Bad nand image
0xD9 SHA_COMPUTE_CB_B Generate CB_B hash
0xDA SHA_VERIFY_CB_B Verify CB_B hash Bad CB_B signature
0xDB BRANCH_CB_B Branch to CB_B

CB/CB_B/SB

1BL Panics

Hex Name Description Possible Cause
0x81 MACHINECHECK Panic - Machine Check
0x82 DATA_STORAGE Panic - Data Storage
0x83 DATA_SEGMENT Panic - Data Segment
0x84 INSTRUCTION_STORAGE Panic - Instruction Storage
0x85 INSTRUCTION_SEGMENT Panic - Instruction Segment
0x86 EXTERNAL Panic - External CPU interrupt triggered
0x87 ALIGNMENT Panic - Alignment
0x88 PROGRAM Panic - Program Illegal instruction
0x89 FPU_UNAVAILABLE Panic - FPU Unavailable
0x8A DECREMENTER Panic - Decrementer
0x8B HYPERVISOR_DECREMENTER Panic - Hypervisor Decrementer
0x8C SYSTEM_CALL Panic - System Call
0x8D TRACE Panic - Trace
0x8E VPU_UNAVAILABLE Panic - VPU Unavailable
0x8F MAINTENANCE Panic - Maintenance
0x90 VMX_ASSIST Panic - VMX Assist
0x91 THERMAL_MANAGEMENT Panic - Thermal Management
0x92 WRONG_THREAD Panic - Wrong Thread 1BL executed on wrong thread
0x93 TOO_MANY_CORES Panic - Too Many Cores 1BL executer on wrong core
0x94 VERIFY_OFFSET Panic - Verify Offset Bad 2BL offset
0x95 VERIFY_HEADER Panic - Verify Header Bad 2BL header
0x96 SIG_VERIFY Panic - Signature Verify Bad 2BL signature
0x97 NONHOST_RESUME_STATUS Panic - Non Host Resume Status
0x98 NEXT_STAGE_SIZE Panic - Next Stage Size 2BL size too large
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