Secondary Error Codes: Difference between revisions

Revision as of 23:59, 5 January 2023

SMC Errors

These errors are generated by the System Management Controller.

0001

ANA_V12P0_PWRGD is driven high by the ANA (later HANA) as long as the V_12P0 rail is within tolerance. If V_12P0 ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter EC_FATAL and the 0001 code to be displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x01	ERROR_V_12P0	ANA_V12P0_PWRGD negated unexpectedly	EC_FATAL	0001

0002

VREG_CPU_PWRGD is driven high by the V_CPUCORE controller as long as the rail is within tolerance. If V_CPUCORE ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter EC_FATAL and the 0002 code to be displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x02	ERROR_V_CPUCORE	VREG_CPU_PWRGD negated unexpectedly	EC_FATAL	0002

0003

Xbox 360 (Original)

VREG_GPU_PWRGD is driven high by the V_GPUCORE controller as long as the rail is within tolerance. If V_GPUCORE ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter EC_FATAL and the 0003 code to be displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x03	ERROR_V_GPUCORE	VREG_GPU_PWRGD negated unexpectedly	EC_FATAL	0003

Xbox 360 S and Xbox 360 E

VREG_V3P3_PWRGD is driven high by the V_3P3 controller as long as the rail is within tolerance. If V_3P3 ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter EC_FATAL and the 0003 code to be displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x03	ERROR_V_3P3	VREG_V3P3_PWRGD negated unexpectedly	EC_FATAL	0003

0010

The SMC communicates with the ANA/HANA via the SMBus. If communication is lost, the SMC enters EC_FATAL and the 0010 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x04	ERROR_NO_ANA	ANA/HANA is not responding to reads or writes	EC_FATAL	0010

0011

The SMC monitors the CPU thermal diode as reported by the ANA/HANA. If the CPU temperature exceeds the Trip Temperature defined in the SMC Config, the SMC enters EC_THERMAL and the 0011 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x05	ERROR_THERMAL_CPU	CPU thermal overload	EC_THERMAL	Thermal Overload

0012

The SMC monitors the GPU thermal diode as reported by the ANA/HANA. If the GPU temperature exceeds the Trip Temperature defined in the SMC Config, the SMC enters EC_THERMAL and the 0012 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x06	ERROR_THERMAL_GPU	GPU thermal overload	EC_THERMAL	Thermal Overload

0013

The SMC monitors the eDRAM thermal diode as reported by the ANA/HANA. If the eDRAM temperature exceeds the Trip Temperature defined in the SMC Config, the SMC enters EC_THERMAL and the 0013 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x07	ERROR_THERMAL_EDRAM	eDRAM thermal overload	EC_THERMAL	Thermal Overload

0020

After GPU power and clocking are available, the SMC starts seqUnReset which releases the GPU from reset. It then waits for the GPU to assert GPU_RST_DONE. If the GPU_RST_DONE signal is not asserted in the time allotted, EC_BOOT will be reported. The SMC will retry 4 more times. If on the final attempt, GPU_RST_DONE is still not asserted, the SMC remains in EC_BOOT and the 0020 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x08	ERROR_GPU_RST_DONE	GPU_RST_DONE signal not asserted after seqUnReset time passed	EC_BOOT	0020

0021

After receiving GPU_RST_DONE during seqUnReset, the SMC monitors the PCIe L0 status and waits for the link to enter the L0 state. If the link does not enter the L0 state in the time allotted, EC_BOOT will be reported. The SMC will retry 4 more times. The SMC will retry 4 more times. If on the final attempt, the link still does not enter L0 state, the SMC remains in EC_BOOT and the 0021 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x09	ERROR_NO_PCIE	PCIe link did not enter L0 after seqUnReset time passed	EC_BOOT	0021

0022

After the PCIe link has entered the L0 state during seqUnReset, the SMC releases the CPU from reset. The CPU will run the Bootloaders and start the XSS. When the XSS starts, it will attempt to retrieve the power up cause from the SMC. If the SMC does not receive GetPowerUpCause in the time allotted, EC_BOOT will be reported. The SMC will retry 4 more times. If on the final attempt, GetPowerUpCause is still not received, the SMC remains in EC_BOOT and the 0022 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x0A	ERROR_NO_HANDSHAKE	CPU did not send GetPowerUpCause to SMC	EC_BOOT	0022

0023

Xenon

The SMC communicates with the Backup Clock Generator via the SMBus. If communication is lost, the SMC enters EC_FATAL and the 0023 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x0B	ERROR_NO_CLOCKCHIP	Clock chip is not responding to reads or writes	EC_FATAL	0023

Xbox 360 S and Xbox 360 E

VREG_VEDRAM_PWRGD is driven high by the V_CPUEDRAM controller as long as the rail is within tolerance. If V_CPUEDRAM ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter EC_FATAL and the 0023 code to be displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x0B	ERROR_V_CPUEDRAM	VREG_VEDRAM_PWRGD negated unexpectedly	EC_FATAL	0023

0030

The SMC communicates with the ANA/HANA via the SMBus. If the thermal registers read as zero, the SMC enters EC_FATAL and the 0030 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x0C	ERROR_NO_TEMPERATURES	CPU did not send GetPowerUpCause to SMC	EC_FATAL	0030

0031

Xbox 360 (Original)

VREG_V5P0_VMEM_PWRGD is driven high by the V_5P0/V_MEM controller as long as the rail is within tolerance. If V_5P0 or V_MEM ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter EC_FATAL and the 0031 code to be displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x0D	ERROR_V_5P0_V_MEM	VREG_V5P0_VMEM_PWRGD negated unexpectedly	EC_FATAL	0031

Xbox 360 S and Xbox 360 E

VREG_V5P0_PWRGD is driven high by the V_5P0 controller as long as the rail is within tolerance. If V_5P0 ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter EC_FATAL and the 0031 code to be displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x0D	ERROR_V_5P0	VREG_V5P0_PWRGD negated unexpectedly	EC_FATAL	0031

0032

Xbox 360 S and Xbox 360 E

VREG_CPUCORE_VCS_PWRGD is driven high by the V_CPUVCS controller as long as the rail is within tolerance. If V_CPUVCS ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter EC_FATAL and the 0032 code to be displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x0E	ERROR_V_CPUVCS	VREG_CPUCORE_VCS_PWRGD negated unexpectedly	EC_FATAL	0032

0033

Xbox 360 S and Xbox 360 E

VREG_VMEM_PWRGD is driven high by the V_MEM controller as long as the rail is within tolerance. If V_MEM ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter EC_FATAL and the 0033 code to be displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x0F	ERROR_V_MEM	VREG_VMEM_PWRGD negated unexpectedly	EC_FATAL	0033

XSS Errors

0100

The 2BL tries to retrieve the vendor ID from each memory chip. If any of the IDs cannot be read or mismatch, EC_XSS will be reported. The SMC will retry 4 more times. If on the final attempt, the IDs still cannot be read or mismatch, the SMC remains in EC_XSS and the 0100 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x10	ERROR_NBINIT_MEM_VENDOR_ID	Memory vendor ID read failed or mismatched	EC_XSS	Repair Guides/0100

0101

During 2BL memory initialization, if data cannot be written for read strobe training, EC_XSS will be reported. The SMC will retry 4 more times. If on the final attempt, data still cannot be written, the SMC remains in EC_XSS and the 0101 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x11	ERROR_NBINIT_MEM_READ_STROBE_DATA_WRITE	Unable to write data for read strobe training	EC_XSS	Repair Guides/0101

0102

During 2BL memory initialization, if read strobe delay training fails, EC_XSS will be reported. The SMC will retry 4 more times. If on the final attempt, training still fails, the SMC remains in EC_XSS and the 0102 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x12	ERROR_NBINIT_MEM_READ_STROBE_DELAY_TRAINING	Memory read strobe delay training failed	EC_XSS	Repair Guides/0102

0103

During 2BL memory initialization, if write strobe delay training fails, EC_XSS will be reported. The SMC will retry 4 more times. If on the final attempt, training still fails, the SMC remains in EC_XSS and the 0103 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x13	ERROR_NBINIT_MEM_WRITE_STROBE_DELAY_TRAINING	Memory write strobe delay training failed	EC_XSS	Repair Guides/0103

0110

During 2BL memory initialization, if a memory addressing line fails, EC_XSS will be reported. The SMC will retry 4 more times. If on the final attempt, a memory addressing line still fails, the SMC remains in EC_XSS and the 0110 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x14	ERROR_MEMORY_ADDRESSING	Memory address line failed or unresponsive	EC_XSS	Repair Guides/0110

0111

During 2BL memory initialization, if a memory data line fails, EC_XSS will be reported. The SMC will retry 4 more times. If on the final attempt, a memory data line still fails, the SMC remains in EC_XSS and the 0111 code is displayed on the front panel.

Hex	Name	Description	Type	Repair Guide
0x15	ERROR_MEMORY_DATA	Memory data line failed or unresponsive	EC_XSS	Repair Guides/0111

@@ Line 17: / Line 17: @@
 === 0001 ===
-ANA_V12P0_PWRGD is driven high by the [[ANA]] (later [[HANA]]) as long as the [[Power Rails#V_12P0|V_12P0]] rail is within tolerance. If V_12P0 ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Codes#EC_FATAL|EC_FATAL]] and the 0001 code to be displayed on the front panel.
+ANA_V12P0_PWRGD is driven high by the [[ANA]] (later [[HANA]]) as long as the [[Power Rails#V_12P0|V_12P0]] rail is within tolerance. If V_12P0 ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Types#EC_FATAL|EC_FATAL]] and the 0001 code to be displayed on the front panel.
 {|class="wikitable"
@@ Line 26: / Line 26: @@
 === 0002 ===
-VREG_CPU_PWRGD is driven high by the [[Power Rails#V_CPUCORE|V_CPUCORE]] controller as long as the rail is within tolerance. If V_CPUCORE ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Codes#EC_FATAL|EC_FATAL]] and the 0002 code to be displayed on the front panel.
+VREG_CPU_PWRGD is driven high by the [[Power Rails#V_CPUCORE|V_CPUCORE]] controller as long as the rail is within tolerance. If V_CPUCORE ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Types#EC_FATAL|EC_FATAL]] and the 0002 code to be displayed on the front panel.
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@@ Line 36: / Line 36: @@
 === 0003 ===
 ;[[Xbox 360 (Original)]]
-VREG_GPU_PWRGD is driven high by the [[Power Rails#V_GPUCORE|V_GPUCORE]] controller as long as the rail is within tolerance. If V_GPUCORE ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Codes#EC_FATAL|EC_FATAL]] and the 0003 code to be displayed on the front panel.
+VREG_GPU_PWRGD is driven high by the [[Power Rails#V_GPUCORE|V_GPUCORE]] controller as long as the rail is within tolerance. If V_GPUCORE ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Types#EC_FATAL|EC_FATAL]] and the 0003 code to be displayed on the front panel.
 {|class="wikitable"
@@ Line 45: / Line 45: @@
 ;[[Xbox 360 S]] and [[Xbox 360 E]]
-VREG_V3P3_PWRGD is driven high by the [[Power Rails#V_3P3|V_3P3]] controller as long as the rail is within tolerance. If V_3P3 ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Codes#EC_FATAL|EC_FATAL]] and the 0003 code to be displayed on the front panel.
+VREG_V3P3_PWRGD is driven high by the [[Power Rails#V_3P3|V_3P3]] controller as long as the rail is within tolerance. If V_3P3 ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Types#EC_FATAL|EC_FATAL]] and the 0003 code to be displayed on the front panel.
 {|class="wikitable"
@@ Line 54: / Line 54: @@
 === 0010 ===
-The [[SMC]] communicates with the [[ANA]]/[[HANA]] via the SMBus. If communication is lost, the SMC enters [[Error Codes#EC_FATAL|EC_FATAL]] and the 0010 code is displayed on the front panel.
+The [[SMC]] communicates with the [[ANA]]/[[HANA]] via the SMBus. If communication is lost, the SMC enters [[Error Types#EC_FATAL|EC_FATAL]] and the 0010 code is displayed on the front panel.
 {|class="wikitable"
@@ Line 63: / Line 63: @@
 === 0011 ===
-The [[SMC]] monitors the CPU thermal diode as reported by the [[ANA]]/[[HANA]]. If the CPU temperature exceeds the [[Thermal Algorithm#Trip Temperatures|Trip Temperature]] defined in the [[SMC Config]], the SMC enters [[Error Codes#EC_THERMAL|EC_THERMAL]] and the 0011 code is displayed on the front panel.
+The [[SMC]] monitors the CPU thermal diode as reported by the [[ANA]]/[[HANA]]. If the CPU temperature exceeds the [[Thermal Algorithm#Trip Temperatures|Trip Temperature]] defined in the [[SMC Config]], the SMC enters [[Error Types#EC_THERMAL|EC_THERMAL]] and the 0011 code is displayed on the front panel.
 {|class="wikitable"
@@ Line 72: / Line 72: @@
 === 0012 ===
-The [[SMC]] monitors the GPU thermal diode as reported by the [[ANA]]/[[HANA]]. If the GPU temperature exceeds the [[Thermal Algorithm#Trip Temperatures|Trip Temperature]] defined in the [[SMC Config]], the SMC enters [[Error Codes#EC_THERMAL|EC_THERMAL]] and the 0012 code is displayed on the front panel.
+The [[SMC]] monitors the GPU thermal diode as reported by the [[ANA]]/[[HANA]]. If the GPU temperature exceeds the [[Thermal Algorithm#Trip Temperatures|Trip Temperature]] defined in the [[SMC Config]], the SMC enters [[Error Types#EC_THERMAL|EC_THERMAL]] and the 0012 code is displayed on the front panel.
 {|class="wikitable"
@@ Line 81: / Line 81: @@
 === 0013 ===
-The [[SMC]] monitors the eDRAM thermal diode as reported by the [[ANA]]/[[HANA]]. If the eDRAM temperature exceeds the [[Thermal Algorithm#Trip Temperatures|Trip Temperature]] defined in the [[SMC Config]], the SMC enters [[Error Codes#EC_THERMAL|EC_THERMAL]] and the 0013 code is displayed on the front panel.
+The [[SMC]] monitors the eDRAM thermal diode as reported by the [[ANA]]/[[HANA]]. If the eDRAM temperature exceeds the [[Thermal Algorithm#Trip Temperatures|Trip Temperature]] defined in the [[SMC Config]], the SMC enters [[Error Types#EC_THERMAL|EC_THERMAL]] and the 0013 code is displayed on the front panel.
 {|class="wikitable"
@@ Line 90: / Line 90: @@
 === 0020 ===
-After [[GPU]] power and clocking are available, the [[SMC]] starts [[SMC#seqUnReset|seqUnReset]] which releases the GPU from reset. It then waits for the GPU to assert GPU_RST_DONE. If the GPU_RST_DONE signal is not asserted in the time allotted, [[Error Codes#EC_BOOT|EC_BOOT]] will be reported. The SMC will retry 4 more times. If on the final attempt, GPU_RST_DONE is still not asserted, the SMC remains in EC_BOOT and the 0020 code is displayed on the front panel.
+After [[GPU]] power and clocking are available, the [[SMC]] starts [[SMC#seqUnReset|seqUnReset]] which releases the GPU from reset. It then waits for the GPU to assert GPU_RST_DONE. If the GPU_RST_DONE signal is not asserted in the time allotted, [[Error Types#EC_BOOT|EC_BOOT]] will be reported. The SMC will retry 4 more times. If on the final attempt, GPU_RST_DONE is still not asserted, the SMC remains in EC_BOOT and the 0020 code is displayed on the front panel.
 {|class="wikitable"
@@ Line 99: / Line 99: @@
 === 0021 ===
-After receiving GPU_RST_DONE during [[SMC#seqUnReset|seqUnReset]], the [[SMC]] monitors the [[PCIe]] L0 status and waits for the link to enter the L0 state. If the link does not enter the L0 state in the time allotted, [[Error Codes#EC_BOOT|EC_BOOT]] will be reported. The SMC will retry 4 more times. The SMC will retry 4 more times. If on the final attempt, the link still does not enter L0 state, the SMC remains in EC_BOOT and the 0021 code is displayed on the front panel.
+After receiving GPU_RST_DONE during [[SMC#seqUnReset|seqUnReset]], the [[SMC]] monitors the [[PCIe]] L0 status and waits for the link to enter the L0 state. If the link does not enter the L0 state in the time allotted, [[Error Types#EC_BOOT|EC_BOOT]] will be reported. The SMC will retry 4 more times. The SMC will retry 4 more times. If on the final attempt, the link still does not enter L0 state, the SMC remains in EC_BOOT and the 0021 code is displayed on the front panel.
 {|class="wikitable"
@@ Line 108: / Line 108: @@
 === 0022 ===
-After the [[PCIe]] link has entered the L0 state during [[SMC#seqUnReset|seqUnReset]], the SMC releases the [[CPU]] from reset. The CPU will run the [[Bootloaders]] and start the [[XSS]]. When the XSS starts, it will attempt to retrieve the power up cause from the SMC. If the SMC does not receive GetPowerUpCause in the time allotted, [[Error Codes#EC_BOOT|EC_BOOT]] will be reported. The SMC will retry 4 more times. If on the final attempt, GetPowerUpCause is still not received, the SMC remains in EC_BOOT and the 0022 code is displayed on the front panel.
+After the [[PCIe]] link has entered the L0 state during [[SMC#seqUnReset|seqUnReset]], the SMC releases the [[CPU]] from reset. The CPU will run the [[Bootloaders]] and start the [[XSS]]. When the XSS starts, it will attempt to retrieve the power up cause from the SMC. If the SMC does not receive GetPowerUpCause in the time allotted, [[Error Types#EC_BOOT|EC_BOOT]] will be reported. The SMC will retry 4 more times. If on the final attempt, GetPowerUpCause is still not received, the SMC remains in EC_BOOT and the 0022 code is displayed on the front panel.
 {|class="wikitable"
@@ Line 118: / Line 118: @@
 === 0023 ===
 ;[[Xenon (Motherboard)|Xenon]]
-The [[SMC]] communicates with the [[Backup Clock Generator]] via the SMBus. If communication is lost, the SMC enters [[Error Codes#EC_FATAL|EC_FATAL]] and the 0023 code is displayed on the front panel.
+The [[SMC]] communicates with the [[Backup Clock Generator]] via the SMBus. If communication is lost, the SMC enters [[Error Types#EC_FATAL|EC_FATAL]] and the 0023 code is displayed on the front panel.
 {|class="wikitable"
@@ Line 127: / Line 127: @@
 ;[[Xbox 360 S]] and [[Xbox 360 E]]
-VREG_VEDRAM_PWRGD is driven high by the [[Power Rails#V_CPUEDRAM|V_CPUEDRAM]] controller as long as the rail is within tolerance. If V_CPUEDRAM ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Codes#EC_FATAL|EC_FATAL]] and the 0023 code to be displayed on the front panel.
+VREG_VEDRAM_PWRGD is driven high by the [[Power Rails#V_CPUEDRAM|V_CPUEDRAM]] controller as long as the rail is within tolerance. If V_CPUEDRAM ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Types#EC_FATAL|EC_FATAL]] and the 0023 code to be displayed on the front panel.
 {|class="wikitable"
@@ Line 136: / Line 136: @@
 === 0030 ===
-The [[SMC]] communicates with the [[ANA]]/[[HANA]] via the SMBus. If the thermal registers read as zero, the SMC enters [[Error Codes#EC_FATAL|EC_FATAL]] and the 0030 code is displayed on the front panel.
+The [[SMC]] communicates with the [[ANA]]/[[HANA]] via the SMBus. If the thermal registers read as zero, the SMC enters [[Error Types#EC_FATAL|EC_FATAL]] and the 0030 code is displayed on the front panel.
 {|class="wikitable"
@@ Line 146: / Line 146: @@
 === 0031 ===
 ;[[Xbox 360 (Original)]]
-VREG_V5P0_VMEM_PWRGD is driven high by the [[Power Rails#V_5P0|V_5P0]]/[[Power Rails#V_MEM|V_MEM]] controller as long as the rail is within tolerance. If V_5P0 or V_MEM ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Codes#EC_FATAL|EC_FATAL]] and the 0031 code to be displayed on the front panel.
+VREG_V5P0_VMEM_PWRGD is driven high by the [[Power Rails#V_5P0|V_5P0]]/[[Power Rails#V_MEM|V_MEM]] controller as long as the rail is within tolerance. If V_5P0 or V_MEM ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Types#EC_FATAL|EC_FATAL]] and the 0031 code to be displayed on the front panel.
 {|class="wikitable"
@@ Line 155: / Line 155: @@
 ;[[Xbox 360 S]] and [[Xbox 360 E]]
-VREG_V5P0_PWRGD is driven high by the [[Power Rails#V_5P0|V_5P0]] controller as long as the rail is within tolerance. If V_5P0 ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Codes#EC_FATAL|EC_FATAL]] and the 0031 code to be displayed on the front panel.
+VREG_V5P0_PWRGD is driven high by the [[Power Rails#V_5P0|V_5P0]] controller as long as the rail is within tolerance. If V_5P0 ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Types#EC_FATAL|EC_FATAL]] and the 0031 code to be displayed on the front panel.
 {|class="wikitable"
@@ Line 165: / Line 165: @@
 === 0032 ===
 ;[[Xbox 360 S]] and [[Xbox 360 E]]
-VREG_CPUCORE_VCS_PWRGD is driven high by the [[Power Rails#V_CPUVCS|V_CPUVCS]] controller as long as the rail is within tolerance. If V_CPUVCS ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Codes#EC_FATAL|EC_FATAL]] and the 0032 code to be displayed on the front panel.
+VREG_CPUCORE_VCS_PWRGD is driven high by the [[Power Rails#V_CPUVCS|V_CPUVCS]] controller as long as the rail is within tolerance. If V_CPUVCS ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Types#EC_FATAL|EC_FATAL]] and the 0032 code to be displayed on the front panel.
 {|class="wikitable"
@@ Line 175: / Line 175: @@
 === 0033 ===
 ;[[Xbox 360 S]] and [[Xbox 360 E]]
-VREG_VMEM_PWRGD is driven high by the [[Power Rails#V_MEM|V_MEM]] controller as long as the rail is within tolerance. If V_MEM ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Codes#EC_FATAL|EC_FATAL]] and the 0033 code to be displayed on the front panel.
+VREG_VMEM_PWRGD is driven high by the [[Power Rails#V_MEM|V_MEM]] controller as long as the rail is within tolerance. If V_MEM ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Error Types#EC_FATAL|EC_FATAL]] and the 0033 code to be displayed on the front panel.
 {|class="wikitable"
@@ Line 186: / Line 186: @@
 === 0100 ===
-The [[2BL]] tries to retrieve the vendor ID from each memory chip. If any of the IDs cannot be read or mismatch, [[Error Codes#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, the IDs still cannot be read or mismatch, the SMC remains in EC_XSS and the 0100 code is displayed on the front panel.
+The [[2BL]] tries to retrieve the vendor ID from each memory chip. If any of the IDs cannot be read or mismatch, [[Error Types#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, the IDs still cannot be read or mismatch, the SMC remains in EC_XSS and the 0100 code is displayed on the front panel.
 {|class="wikitable"
@@ Line 195: / Line 195: @@
 === 0101 ===
-During [[2BL]] memory initialization, if data cannot be written for read strobe training, [[Error Codes#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, data still cannot be written, the SMC remains in EC_XSS and the 0101 code is displayed on the front panel.
+During [[2BL]] memory initialization, if data cannot be written for read strobe training, [[Error Types#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, data still cannot be written, the SMC remains in EC_XSS and the 0101 code is displayed on the front panel.
 {|class="wikitable"
@@ Line 204: / Line 204: @@
 === 0102 ===
-During [[2BL]] memory initialization, if read strobe delay training fails, [[Error Codes#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, training still fails, the SMC remains in EC_XSS and the 0102 code is displayed on the front panel.
+During [[2BL]] memory initialization, if read strobe delay training fails, [[Error Types#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, training still fails, the SMC remains in EC_XSS and the 0102 code is displayed on the front panel.
 {|class="wikitable"
@@ Line 213: / Line 213: @@
 === 0103 ===
-During [[2BL]] memory initialization, if write strobe delay training fails, [[Error Codes#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, training still fails, the SMC remains in EC_XSS and the 0103 code is displayed on the front panel.
+During [[2BL]] memory initialization, if write strobe delay training fails, [[Error Types#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, training still fails, the SMC remains in EC_XSS and the 0103 code is displayed on the front panel.
 {|class="wikitable"
@@ Line 222: / Line 222: @@
 === 0110 ===
-During [[2BL]] memory initialization, if a memory addressing line fails, [[Error Codes#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, a memory addressing line still fails, the SMC remains in EC_XSS and the 0110 code is displayed on the front panel.
+During [[2BL]] memory initialization, if a memory addressing line fails, [[Error Types#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, a memory addressing line still fails, the SMC remains in EC_XSS and the 0110 code is displayed on the front panel.
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@@ Line 231: / Line 231: @@
 === 0111 ===
-During [[2BL]] memory initialization, if a memory data line fails, [[Error Codes#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, a memory data line still fails, the SMC remains in EC_XSS and the 0111 code is displayed on the front panel.
+During [[2BL]] memory initialization, if a memory data line fails, [[Error Types#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, a memory data line still fails, the SMC remains in EC_XSS and the 0111 code is displayed on the front panel.
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v e Error Database
SMC Errors	0001 · 0002 · 0003 · 0010 · 0011 · 0012 · 0013 · 0020 · 0021 · 0022 · 0023 · 0030 · 0031 · 0032 · 0033
XSS Errors	0100 · 0101 · 0102 · 0103 · 0110 · 0111