Template:Motherboard Components: Difference between revisions
Jump to navigation
Jump to search
No edit summary |
No edit summary |
||
| Line 7: | Line 7: | ||
|list1 = {{Navbox subgroup | |list1 = {{Navbox subgroup | ||
|group1 = 90nm | |group1 = 90nm | ||
|list1 = [[Waternoose]] ([[Waternoose#DD1|DD1]]{{dot}}[[Waternoose#DD2|DD2]]{{dot}}[[Waternoose#DD3|DD3]]) | |list1 = [[Shiva]]{dot}}[[Waternoose]] ([[Waternoose#DD1|DD1]]{{dot}}[[Waternoose#DD2|DD2]]{{dot}}[[Waternoose#DD3|DD3]]) | ||
|group2 = 65nm | |group2 = 65nm | ||
|list2 = [[Loki]] | |list2 = [[Loki]] | ||
| Line 58: | Line 58: | ||
|group9 = Misc | |group9 = Misc | ||
|list9 = [[Power Rails]] ([[Power Rails (Original)|Original]]{{dot}}[[Power Rails (S/E)|S/E]]) | |list9 = [[Power Rails]] ([[Power Rails (Original)|Original]]{{dot}}[[Power Rails (S/E)|S/E]]) | ||
}} | }} | ||
<noinclude>[[Category:Main]]</noinclude> | <noinclude>[[Category:Main]]</noinclude> | ||
Revision as of 16:33, 16 June 2023
|group2 = Xenos
(GPU)
|list2 =
90nm | |
|---|---|
80nm | |
65nm |
|group3 = XCGPU |list3 = Valhalla · Winchester CGPU |group4 = Southbridge |list4 = XSB · PSB · KSB |group5 = Analog Chip |list5 = ANA · HANA · Backup Clock Gen |group6 = RAM|list6 =
|group7 = Nand|list7 =
16MB | |
|---|---|
64MB | |
256MB | |
512MB | |
4GB |
|group8 = eMMC |list8 = Hynix H26M31001FPR · SK Hynix H26M31002GPR · Toshiba THGBM5G5A1JBAIR |group9 = Misc |list9 = Power Rails (Original · S/E)
}}