Template:CPU Specs: Difference between revisions
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(Created page with "* 3 two-way SMD-capable RISC cores clocked at 3.2GHz * SIMD: Two VMX128 units * 32KB L1 data cache * 32KB L1 instruction cache * 1MB L2 cache at 1.6 GHz with a 256-bit bus * 21.6GB/s FSB * 768 bits of IBM eFUSE one-time-program memory * ROM and 64KB SRAM for storing the 1BL * Big-endian architecture") |
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* 1MB L2 cache at 1.6 GHz with a 256-bit bus | * 1MB L2 cache at 1.6 GHz with a 256-bit bus | ||
* 21.6GB/s [[FSB]] | * 21.6GB/s [[FSB]] | ||
* 768 bits of IBM [[eFUSE]] | * 768 bits of IBM [[eFUSE]] One-Time-Program memory for [[fusesets]] | ||
* ROM and 64KB SRAM for | * One-Time-Programmable ROM and 64KB SRAM for the [[1BL]] and [[Config Ring]] | ||
* Big-endian architecture | * Big-endian architecture | ||
Latest revision as of 15:02, 13 January 2024
- 3 two-way SMD-capable RISC cores clocked at 3.2GHz
- SIMD: Two VMX128 units
- 32KB L1 data cache
- 32KB L1 instruction cache
- 1MB L2 cache at 1.6 GHz with a 256-bit bus
- 21.6GB/s FSB
- 768 bits of IBM eFUSE One-Time-Program memory for fusesets
- One-Time-Programmable ROM and 64KB SRAM for the 1BL and Config Ring
- Big-endian architecture