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Combined display of all available logs of XenonLibrary. You can narrow down the view by selecting a log type, the username (case-sensitive), or the affected page (also case-sensitive).

• 20:05, 21 December 2022 Octal450 talk contribs created page Template:CPU Specs (Created page with "* 3 two-way SMD-capable RISC cores clocked at 3.2GHz * SIMD: Two VMX128 units * 32KB L1 data cache * 32KB L1 instruction cache * 1MB L2 cache at 1.6 GHz with a 256-bit bus * 21.6GB/s FSB * 768 bits of IBM eFUSE one-time-program memory * ROM and 64KB SRAM for storing the 1BL * Big-endian architecture")