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The '''Titan''' is a development board used during [[Bringup]] of the [[Shiva (CPU)|Shiva]] and [[Waternoose (CPU)#DD1.0|Waternoose DD1.0]] Engineering Sample CPUs. It also allows an IBM RISCWatch to be used to debug and test the processors. | The '''Titan''' is a development board used during [[Bringup]] of the [[Shiva (CPU)|Shiva]] and [[Waternoose (CPU)#DD1.0|Waternoose DD1.0]] Engineering Sample CPUs. It also allows an IBM RISCWatch to be used to debug and test the processors. | ||
== Specifications == | |||
* Xilinx Spartan 3 XC3S200 FPGA | |||
* 128KB Xilinx XCF01S JTAG PROM | |||
* 4 DIP Switches | |||
* 9 3.3V LEDs (Later versions only) | |||
* 50MHz 3.3V Crystal | |||
== Details == | |||
The Titan is powered off the console via the [[Power Rails#V_MEMPORT|V_MEMPORT]] 3.3V and [[Power Rails#V_1P8|V_1P8]] 1.8V rails. The 3.3V is also stepped down to 2.5V and 1.2V. | |||
The 10-pin J_YETI header connects to J8C1, the CPU JTAG header, while the 12-pin J_GPUL header connects to J7G2, the [[Shiva]] JTAG header. | |||
== Gallery == | == Gallery == | ||
Revision as of 15:31, 3 January 2023
 Titan II | |
| Designed By | IBM |
|---|---|
The Titan is a development board used during Bringup of the Shiva and Waternoose DD1.0 Engineering Sample CPUs. It also allows an IBM RISCWatch to be used to debug and test the processors.
Specifications
- Xilinx Spartan 3 XC3S200 FPGA
- 128KB Xilinx XCF01S JTAG PROM
- 4 DIP Switches
- 9 3.3V LEDs (Later versions only)
- 50MHz 3.3V Crystal
Details
The Titan is powered off the console via the V_MEMPORT 3.3V and V_1P8 1.8V rails. The 3.3V is also stepped down to 2.5V and 1.2V.
The 10-pin J_YETI header connects to J8C1, the CPU JTAG header, while the 12-pin J_GPUL header connects to J7G2, the Shiva JTAG header.
Gallery
XeDK 007 with Titan II powered on
