Shiva: Difference between revisions
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{{Infobox Chip | {{Infobox Chip | ||
| name = Shiva | | name = Shiva | ||
| image = X02318-001 | | image = X02318-001.jpg | ||
| image_size = 150px | | image_size = 150px | ||
| caption = Shiva | | caption = Shiva with [[IHS]] | ||
| image2 = X02318-001-delid.jpg | | image2 = X02318-001-delid.jpg | ||
| image2_size = 150px | | image2_size = 150px | ||
| caption2 = Shiva | | caption2 = Shiva without IHS | ||
| partnumber = X02318 | | partnumber = X02318 | ||
| introduced = 2004 | | introduced = 2004 | ||
| Line 13: | Line 13: | ||
| type = CPU | | type = CPU | ||
| arch = PowerPC RISC | | arch = PowerPC RISC | ||
| clockspeed = | | clockspeed = 2GHz | ||
| cores = 1 | | cores = 1 | ||
| process = 90nm | | process = 90nm | ||
| tdp = 67W | | tdp = 67W | ||
| package = Flip-chip BGA899 | | package = Flip-chip BGA899 MCM | ||
| successor = [[XCPU]] | | successor = [[Waternoose]] ([[XCPU]]) | ||
}} | }} | ||
'''Shiva''' is an early internal CPU used for [[Xbox 360]] software development before the [[ | '''Shiva''' is an early internal CPU used for [[Xbox 360]] software development before the [[Waternoose]] was in production. It was not used for game development or testing. It is a Multi-Chip-Module (MCM) containing a PowerPC GPUL core, and the "Yeti" I/O die. | ||
== Specifications == | == Specifications == | ||
* Single PowerPC 970FX RISC (GPUL) core clocked at | [[File:X02318-001-Pads.jpg|thumb|150px|upright|right|Shiva with solder cleaned off]] | ||
* Yeti I/O die to adapt | [[File:X02318-001-BGA-Side.jpg|thumb|150px|upright|right|The strangely shaped solder balls on Shiva]] | ||
* Single PowerPC 970FX RISC (GPUL) core clocked at 2GHz | |||
* Yeti I/O die to adapt GPUL | |||
* 2GB/s [[FSB]] | * 2GB/s [[FSB]] | ||
* 90nm process | * 90nm process | ||
| Line 31: | Line 34: | ||
== Details == | == Details == | ||
Shiva has 2 dies, covered by a thick [[IHS| | Shiva has 2 dies, covered by a thick [[IHS|integrated heat spreader]]. | ||
* The larger die is a PowerPC "GPUL" 970FX core (GigaProcessor UltraLite) | |||
* The smaller die, "Yeti", is an interface with the rest of the [[Xenon (Motherboard)|Xenon]] system | |||
Shiva is also known as DD0.9, a reference to the DD1/DD2/DD3 names used on [[Waternoose]]. | |||
Shiva is | Like other PowerPC 970 series chips, Shiva is not capable of performing [[Power On Reset]] and [[Initial Program Load]] on its own. Systems using this chip have a service processor (for example, IBM's U3 northbridge) to perform these functions. As the [[Xenon (Motherboard)|Xenon]] system does not have such a chip, the [[Titan]] FPGA card was used. A [[Heatsink#Shiva CPU|modified CPU heatsink]] was used in order to account for the height difference from Waternoose. | ||
* Part Number: X02318 | * Part Number: X02318 | ||
{{Motherboard Components}} | {{Motherboard Components}} | ||
[[Category:Motherboard Components]] | [[Category:Motherboard Components]] | ||
Latest revision as of 00:19, 4 October 2024
 Shiva with IHS | |
 Shiva without IHS | |
| Part Number | X02318 |
|---|---|
| Introduced | 2004 |
| Designed By | IBM Microsoft |
| Codename | DD0.9 |
| Type | CPU |
| Clock Speed | 2GHz |
| Instruction Set | PowerPC RISC |
| Cores | 1 |
| Process | 90nm |
| TDP | 67W |
| Package | Flip-chip BGA899 MCM |
| Successor | Waternoose (XCPU) |
Shiva is an early internal CPU used for Xbox 360 software development before the Waternoose was in production. It was not used for game development or testing. It is a Multi-Chip-Module (MCM) containing a PowerPC GPUL core, and the "Yeti" I/O die.
Specifications
- Single PowerPC 970FX RISC (GPUL) core clocked at 2GHz
- Yeti I/O die to adapt GPUL
- 2GB/s FSB
- 90nm process
- 67W TDP
Details
Shiva has 2 dies, covered by a thick integrated heat spreader.
- The larger die is a PowerPC "GPUL" 970FX core (GigaProcessor UltraLite)
- The smaller die, "Yeti", is an interface with the rest of the Xenon system
Shiva is also known as DD0.9, a reference to the DD1/DD2/DD3 names used on Waternoose.
Like other PowerPC 970 series chips, Shiva is not capable of performing Power On Reset and Initial Program Load on its own. Systems using this chip have a service processor (for example, IBM's U3 northbridge) to perform these functions. As the Xenon system does not have such a chip, the Titan FPGA card was used. A modified CPU heatsink was used in order to account for the height difference from Waternoose.
- Part Number: X02318