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__NOTOC__
#REDIRECT [[Errors#Secondary Error Codes]]
{{Navbox
|name        = Secondary Error Codes
|title      = [[Secondary Error Codes]]
|listclass  = hlist
|state      = uncollapsed
|group1    = Information
|list1      = [[Errors]] ([[Errors#Error Behavior|Behavior]]{{dot}}[[Errors#Error Code Identification|Code Identification]]{{dot}}[[Errors#Failure Modes|Failure Modes]])
|group2    = [[#SMC Errors|SMC Errors]]
|list2      = [[#0001|0001]]{{dot}}[[#0002|0002]]{{dot}}[[#0003|0003]]{{dot}}[[#0010|0010]]{{dot}}[[#0011|0011]]{{dot}}[[#0012|0012]]{{dot}}[[#0013|0013]]{{dot}}[[#0020|0020]]{{dot}}[[#0021|0021]]{{dot}}[[#0022|0022]]{{dot}}[[#0023|0023]]{{dot}}[[#0030|0030]]{{dot}}[[#0031|0031]]{{dot}}[[#0032|0032]]{{dot}}[[#0033|0033]]
|group3    = [[#XSS Errors|XSS Errors]]
|list3      = [[#0100|0100]]{{dot}}[[#0101|0101]]{{dot}}[[#0102|0102]]{{dot}}[[#0103|0103]]{{dot}}[[#0110|0110]]{{dot}}[[#0111|0111]]{{dot}}[[#1000|1000]]{{dot}}[[#1001|1001]]{{dot}}[[#1002|1002]]{{dot}}[[#1003|1003]]{{dot}}[[#1010|1010]]{{dot}}[[#1011|1011]]{{dot}}[[#1012|1012]]{{dot}}[[#1013|1013]]{{dot}}[[#1020|1020]]{{dot}}[[#1021|1021]]{{dot}}[[#1022|1022]]{{dot}}[[#1023|1023]]{{dot}}[[#1030|1030]]{{dot}}[[#1031|1031]]{{dot}}[[#1032|1032]]{{dot}}[[#1033|1033]]{{dot}}[[#1100|1100]]{{dot}}[[#1101|1101]]{{dot}}[[#1102|1102]]
|group4    = [[#UEM Errors|UEM Errors]]
|list4      = [[#1000|E 64]]{{dot}}[[#1001|E 65]]{{dot}}[[#1002|E 66]]{{dot}}[[#1003|E 67]]{{dot}}[[#1010|E 68]]{{dot}}[[#1011|E 69]]{{dot}}[[#1012|E 70]]{{dot}}[[#1013|E 71]]{{dot}}[[#1020|E 72]]{{dot}}[[#1021|E 73]]{{dot}}[[#1022|E 74]]{{dot}}[[#1023|E 75]]{{dot}}[[#1030|E 76]]{{dot}}[[#1031|E 77]]{{dot}}[[#1032|E 78]]{{dot}}[[#1033|E 79]]{{dot}}[[#1100|E 80]]{{dot}}[[#1101|E 81]]{{dot}}[[#1102|E 82]]
}}
{{See also|Errors}}
 
== SMC Errors ==
These errors are generated by the [[SMC]].
 
=== 0001 ===
ANA_V12P0_PWRGD is driven high by the [[ANA]] (later [[HANA]]) as long as the V_12P0 rail is within tolerance. If V_12P0 ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Errors#EC_FATAL|EC_FATAL]] and the 0001 code to be displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x01 || ERROR_V_12P0 || ANA_V12P0_PWRGD negated unexpectedly || EC_FATAL || [[Repair Actions/0001|Repair Actions/0001]]
|}
 
=== 0002 ===
VREG_CPU_PWRGD is driven high by the V_CPUCORE controller as long as the rail is within tolerance. If V_CPUCORE ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Errors#EC_FATAL|EC_FATAL]] and the 0002 code to be displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x02 || ERROR_V_CPUCORE || VREG_CPU_PWRGD negated unexpectedly || EC_FATAL || [[Repair Actions/0002|Repair Actions/0002]]
|}
 
=== 0003 ===
;[[Xbox 360 (Original)]]
VREG_GPU_PWRGD is driven high by the V_GPUCORE controller as long as the rail is within tolerance. If V_GPUCORE ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Errors#EC_FATAL|EC_FATAL]] and the 0003 code to be displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x03 || ERROR_V_GPUCORE || VREG_GPU_PWRGD negated unexpectedly || EC_FATAL || [[Repair Actions/0003|Repair Actions/0003]]
|}
 
;[[Xbox 360 S]] and [[Xbox 360 E]]
VREG_V3P3_PWRGD is driven high by the V_3P3 controller as long as the rail is within tolerance. If V_3P3 ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Errors#EC_FATAL|EC_FATAL]] and the 0003 code to be displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x03 || ERROR_V_3P3 || VREG_V3P3_PWRGD negated unexpectedly || EC_FATAL || [[Repair Actions/0003#S and E|Repair Actions/0003]]
|}
 
=== 0010 ===
The [[SMC]] communicates with the [[ANA]]/[[HANA]] via the SMBus. If communication is lost, the SMC enters [[Errors#EC_FATAL|EC_FATAL]] and the 0010 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x04 || ERROR_NO_ANA || [[ANA]]/[[HANA]] is not responding to reads or writes || EC_FATAL || [[Repair Actions/0010|Repair Actions/0010]]
|}
 
=== 0011 ===
The [[SMC]] monitors the CPU thermal diode as reported by the [[ANA]]/[[HANA]]. If the CPU temperature exceeds the [[Thermal Algorithm#Trip Temperatures|Trip Temperature]] defined in the [[SMC Config]], the SMC enters [[Errors#EC_THERMAL|EC_THERMAL]] and the 0011 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x05 || ERROR_THERMAL_CPU || CPU thermal overload || EC_THERMAL || [[Repair Actions/Thermal Overload]]
|}
 
=== 0012 ===
The [[SMC]] monitors the GPU thermal diode as reported by the [[ANA]]/[[HANA]]. If the GPU temperature exceeds the [[Thermal Algorithm#Trip Temperatures|Trip Temperature]] defined in the [[SMC Config]], the SMC enters [[Errors#EC_THERMAL|EC_THERMAL]] and the 0012 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x06 || ERROR_THERMAL_GPU || GPU thermal overload || EC_THERMAL || [[Repair Actions/Thermal Overload]]
|}
 
=== 0013 ===
The [[SMC]] monitors the eDRAM thermal diode as reported by the [[ANA]]/[[HANA]]. If the eDRAM temperature exceeds the [[Thermal Algorithm#Trip Temperatures|Trip Temperature]] defined in the [[SMC Config]], the SMC enters [[Errors#EC_THERMAL|EC_THERMAL]] and the 0013 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x07 || ERROR_THERMAL_EDRAM || eDRAM thermal overload || EC_THERMAL || [[Repair Actions/Thermal Overload]]
|}
 
=== 0020 ===
After [[GPU]] power and clocking are available, the [[SMC]] starts [[SMC#seqUnReset|seqUnReset]] which releases the GPU from reset. It then waits for the GPU to assert GPU_RST_DONE. If the GPU_RST_DONE signal is not asserted in the time allotted, [[Errors#EC_BOOT|EC_BOOT]] will be reported. The SMC will retry 4 more times. If on the final attempt, GPU_RST_DONE is still not asserted, the SMC remains in EC_BOOT and the 0020 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x08 || ERROR_GPU_RST_DONE || GPU_RST_DONE signal not asserted after seqUnReset time passed || EC_BOOT || [[Repair Actions/0020|Repair Actions/0020]]
|}
 
=== 0021 ===
After receiving GPU_RST_DONE during [[SMC#seqUnReset|seqUnReset]], the [[SMC]] monitors the [[PCIe]] L0 status and waits for the link to enter the L0 state. If the link does not enter the L0 state in the time allotted, [[Errors#EC_BOOT|EC_BOOT]] will be reported. The SMC will retry 4 more times. The SMC will retry 4 more times. If on the final attempt, the link still does not enter L0 state, the SMC remains in EC_BOOT and the 0021 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x09 || ERROR_NO_PCIE || PCIe link did not enter L0 after seqUnReset time passed || EC_BOOT || [[Repair Actions/0021|Repair Actions/0021]]
|}
 
=== 0022 ===
After the [[PCIe]] link has entered the L0 state during [[SMC#seqUnReset|seqUnReset]], the SMC releases the [[CPU]] from reset. The CPU will run the [[Bootloaders]] and start the [[XSS]]. When the XSS starts, it will attempt to retrieve the power up cause from the SMC. If the SMC does not receive GetPowerUpCause in the time allotted, [[Errors#EC_BOOT|EC_BOOT]] will be reported. The SMC will retry 4 more times. If on the final attempt, GetPowerUpCause is still not received, the SMC remains in EC_BOOT and the 0022 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x0A || ERROR_NO_HANDSHAKE || CPU did not send GetPowerUpCause to SMC || EC_BOOT || [[Repair Actions/0022|Repair Actions/0022]]
|}
 
=== 0023 ===
;[[Xenon (Motherboard)|Xenon]]
The [[SMC]] communicates with the [[Backup Clock Generator]] via the SMBus. If communication is lost, the SMC enters [[Errors#EC_FATAL|EC_FATAL]] and the 0023 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x0B || ERROR_NO_CLOCKCHIP || Clock chip is not responding to reads or writes || EC_FATAL || [[Repair Actions/0023|Repair Actions/0023]]
|}
 
;[[Xbox 360 S]] and [[Xbox 360 E]]
VREG_VEDRAM_PWRGD is driven high by the V_CPUEDRAM controller as long as the rail is within tolerance. If V_CPUEDRAM ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Errors#EC_FATAL|EC_FATAL]] and the 0023 code to be displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x0B || ERROR_V_CPUEDRAM || VREG_VEDRAM_PWRGD negated unexpectedly || EC_FATAL || [[Repair Actions/0023#S and E|Repair Actions/0023]]
|}
 
=== 0030 ===
The [[SMC]] communicates with the [[ANA]]/[[HANA]] via the SMBus. If the thermal registers read as zero, the SMC enters [[Errors#EC_FATAL|EC_FATAL]] and the 0030 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x0C || ERROR_NO_TEMPERATURES || CPU did not send GetPowerUpCause to SMC || EC_FATAL || [[Repair Actions/0030|Repair Actions/0030]]
|}
 
=== 0031 ===
;[[Xbox 360 (Original)]]
VREG_V5P0_VMEM_PWRGD is driven high by the V_5P0/V_MEM controller as long as the rail is within tolerance. If V_5P0 or V_MEM ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Errors#EC_FATAL|EC_FATAL]] and the 0031 code to be displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x0D || ERROR_V_5P0_V_MEM || VREG_V5P0_VMEM_PWRGD negated unexpectedly || EC_FATAL || [[Repair Actions/0031|Repair Actions/0031]]
|}
 
;[[Xbox 360 S]] and [[Xbox 360 E]]
VREG_V5P0_PWRGD is driven high by the V_5P0 controller as long as the rail is within tolerance. If V_5P0 ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Errors#EC_FATAL|EC_FATAL]] and the 0031 code to be displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x0D || ERROR_V_5P0 || VREG_V5P0_PWRGD negated unexpectedly || EC_FATAL || [[Repair Actions/0031#S and E|Repair Actions/0031]]
|}
 
=== 0032 ===
;[[Xbox 360 S]] and [[Xbox 360 E]]
VREG_CPUCORE_VCS_PWRGD is driven high by the V_CPUVCS controller as long as the rail is within tolerance. If V_CPUVCS ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Errors#EC_FATAL|EC_FATAL]] and the 0032 code to be displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x0E || ERROR_V_CPUVCS || VREG_CPUCORE_VCS_PWRGD negated unexpectedly || EC_FATAL || [[Repair Actions/0032#S and E|Repair Actions/0032]]
|}
 
=== 0033 ===
;[[Xbox 360 S]] and [[Xbox 360 E]]
VREG_VMEM_PWRGD is driven high by the V_MEM controller as long as the rail is within tolerance. If V_MEM ever drops out of tolerance, the signal is de-asserted, causing the [[SMC]] to enter [[Errors#EC_FATAL|EC_FATAL]] and the 0033 code to be displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x0F || ERROR_V_MEM || VREG_VMEM_PWRGD negated unexpectedly || EC_FATAL || [[Repair Actions/0033#S and E|Repair Actions/0033]]
|}
 
== XSS Errors ==
These errors are generated by the [[XSS]] and reported to the [[SMC]].
 
=== 0100 ===
The [[2BL]] tries to retrieve the vendor ID from each memory chip. If any of the IDs cannot be read or mismatch, [[Errors#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, the IDs still cannot be read or mismatch, the SMC remains in EC_XSS and the 0100 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x10 || ERROR_NBINIT_MEM_VENDOR_ID || Memory vendor ID read failed or mismatched || EC_XSS || [[Repair Actions/0100]]
|}
 
=== 0101 ===
During [[2BL]] memory initialization, if data cannot be written for read strobe training, [[Errors#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, data still cannot be written, the SMC remains in EC_XSS and the 0101 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x11 || ERROR_NBINIT_MEM_READ_STROBE_DATA_WRITE || Unable to write data for read strobe training || EC_XSS || [[Repair Actions/0101]]
|}
 
=== 0102 ===
During [[2BL]] memory initialization, if read strobe delay training fails, [[Errors#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, training still fails, the SMC remains in EC_XSS and the 0102 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x12 || ERROR_NBINIT_MEM_READ_STROBE_DELAY_TRAINING || Memory read strobe delay training failed || EC_XSS || [[Repair Actions/0102]]
|}
 
=== 0103 ===
During [[2BL]] memory initialization, if write strobe delay training fails, [[Errors#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, training still fails, the SMC remains in EC_XSS and the 0103 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x13 || ERROR_NBINIT_MEM_WRITE_STROBE_DELAY_TRAINING || Memory write strobe delay training failed || EC_XSS || [[Repair Actions/0103]]
|}
 
=== 0110 ===
During [[2BL]] memory initialization, if a memory addressing line fails, [[Errors#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, a memory addressing line still fails, the SMC remains in EC_XSS and the 0110 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x14 || ERROR_MEMORY_ADDRESSING || Memory address line failed or unresponsive || EC_XSS || [[Repair Actions/0110]]
|}
 
=== 0111 ===
During [[2BL]] memory initialization, if a memory data line fails, [[Errors#EC_XSS|EC_XSS]] will be reported. The SMC will retry 4 more times. If on the final attempt, a memory data line still fails, the SMC remains in EC_XSS and the 0111 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! Name !! Description !! Type !! Repair Guide
|-
| 0x15 || ERROR_MEMORY_DATA || Memory data line failed or unresponsive || EC_XSS || [[Repair Actions/0111]]
|}
 
----
 
=== 1000 ===
Occurs if [[kernel]] communications to the [[DVD Drive]] time out. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 64 [[UEM]] will be displayed, and the 1000 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x40 || E 64 || ERROR_XSS_CDROM_TIMED_OUT || Kernel DVD drive communications timed out || EC_XSS || [[Repair Actions/1000]]
|}
 
=== 1001 ===
Occurs if the [[kernel]] cannot configure the [[DVD Drive]] for Direct Memory Access mode. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 65 [[UEM]] will be displayed, and the 1001 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x41 || E 65 || ERROR_XSS_CDROM_NOT_DMA_CONFIGURED || Kernel could not configure DVD drive for DMA mode || EC_XSS || [[Repair Actions/1001]]
|}
 
=== 1002 ===
Occurs if the [[kernel]] cannot create a device instance for the [[DVD Drive]]. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 66 [[UEM]] will be displayed, and the 1002 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x42 || E 66 || ERROR_XSS_CDROM_COULD_NOT_CREATE_DEVICE || Kernel could not create DVD drive instance || EC_XSS || [[Repair Actions/1002]]
|}
 
=== 1003 ===
Occurs if [[kernel]] communications to the [[Hard Drive]] time out. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 67 [[UEM]] will be displayed, and the 1003 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x43 || E 67 || ERROR_XSS_HDD_TIMED_OUT || Kernel HDD communications timed out || EC_XSS || [[Repair Actions/1003]]
|}
 
=== 1010 ===
Occurs if the [[kernel]] cannot configure the [[Hard Drive]] for Direct Memory Access mode. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 68 [[UEM]] will be displayed, and the 1010 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x44 || E 68 || ERROR_XSS_HDD_NOT_DMA_CONFIGURED || Kernel could not configure HDD for DMA mode || EC_XSS || [[Repair Actions/1010]]
|}
 
=== 1011 ===
Occurs if the [[kernel]] cannot create a device instance for the [[Hard Drive]]. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 69 [[UEM]] will be displayed, and the 1011 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x45 || E 69 || ERROR_XSS_HDD_COULD_NOT_CREATE_DEVICE || Kernel could not create HDD instance || EC_XSS || [[Repair Actions/1011]]
|}
 
=== 1012 ===
Occurs if a [[Hard Drive]] is detected, but the [[kernel]] cannot find or access it. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 70 [[UEM]] will be displayed, and the 1012 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x46 || E 70 || ERROR_XSS_HDD_NOT_FOUND || Kernel couldn't find the HDD || EC_XSS || [[Repair Actions/1012]]
|}
 
=== 1013 ===
Occurs if [[XAM]] cannot find a [[Dashboard]] (dash.xex) to load from the [[Nand]]. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 71 [[UEM]] will be displayed, and the 1013 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x47 || E 71 || ERROR_XSS_XAM_NO_DASH || XAM could not find a dash to load || EC_XSS || [[Repair Actions/1013]]
|}
 
=== 1020 ===
Occurs if the [[SMC Config]] on the [[Nand]] is missing or corrupt. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 72 [[UEM]] will be displayed, and the 1020 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x48 || E 72 || ERROR_SMC_FLASH_CONFIG_CORRUPT || SMC configuration area in the nand is corrupt || EC_XSS || [[Repair Actions/1020]]
|}
 
=== 1021 ===
Occurs if the [[HSIO]] training fails due to an unresponsive or malfunctioning eDRAM. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 73 [[UEM]] will be displayed, and the 1021 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x49 || E 73 || ERROR_HSIO_TRAINING_FAILED || GPU to eDRAM High Speed Link failed || EC_XSS || [[Repair Actions/1021]]
|}
 
=== 1022 ===
;[[Xbox 360 (Original)]]
Occurs if the [[HSIO]] calibration fails due to an unresponsive or malfunctioning eDRAM. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 74 [[UEM]] will be displayed, and the 1022 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x4A || E 74 || ERROR_HSIO_CALIBRATION_FAILED || GPU to eDRAM High Speed Link failed || EC_XSS || [[Repair Actions/1022]]
|}
 
=== 1023 ===
Occurs if the [[Southbridge]] can't communicate with the [[Ethernet PHY]], or the vendor ID of the PHY is incorrect. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 75 [[UEM]] will be displayed, and the 1023 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x4B || E 75 || ERROR_UNEXPECTED_ETHERNET_PHY_VENDOR || Southbridge could not communicate with Ethernet PHY over MDIO/MDC || EC_XSS || [[Repair Actions/1023]]
|}
 
=== 1030 ===
Occurs if the [[Ethernet PHY]] does not complete the reset sequence properly. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 76 [[UEM]] will be displayed, and the 1030 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x4C || E 76 || ERROR_ETHERNET_PHY_RESET_FAIL || Ethernet PHY failed to complete reset || EC_XSS || [[Repair Actions/1030]]
|}
 
=== 1031 ===
Occurs if the [[Southbridge]] can't read from or write to the [[Ethernet PHY]]. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 77 [[UEM]] will be displayed, and the 1031 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x4D || E 77 || ERROR_ETHERNET_PHY_READ_WRITE_FAIL || Could not read from or write to Ethernet PHY || EC_XSS || [[Repair Actions/1031]]
|}
 
=== 1032 ===
Occurs if the [[GPU]] design revision is unsupported by the [[kernel]]. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 78 [[UEM]] will be displayed, and the 1032 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x4E || E 78 || ERROR_UNSUPPORTED_GPU || GPU is wrong revision and not supported || EC_XSS || [[Repair Actions/1032]]
|}
 
=== 1033 ===
Occurs if [[XAM]] cannot found on the [[Nand]]. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 79 [[UEM]] will be displayed, and the 1032 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x4F || E 79 || ERROR_XSS_FLASH_NO_XAM || XAM could not be found on the nand || EC_XSS || [[Repair Actions/1033]]
|}
 
=== 1100 ===
To be determined.
 
=== 1101 ===
Occurs if XeKeysSecuritySaveSettings fails. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 81 [[UEM]] will be displayed, and the 1101 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x51 || E 81 || Unknown || XeKeysSecuritySaveSettings failed || EC_XSS || [[Repair Actions/1101]]
|}
 
=== 1102 ===
;[[Xbox 360 S]] and [[Xbox 360 E]]
Occurs if the [[HSIO]] calibration fails due to an unresponsive or malfunctioning eDRAM. The [[SMC]] enters [[Errors#EC_XSS|EC_XSS]], the E 82 [[UEM]] will be displayed, and the 1102 code is displayed on the front panel.
 
{|class="wikitable"
! Hex !! UEM !! Name !! Description !! Type !! Repair Guide
|-
| 0x52 || E 82 || ERROR_HSIO_CALIBRATION_FAILED || CGPU to eDRAM High Speed Link failed || EC_XSS || [[Repair Actions/1102]]
|}
 
{{Debug and Repair}}

Latest revision as of 19:53, 5 May 2023

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