Secondary Error Codes: Difference between revisions
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=== 0001 === | === 0001 === | ||
ANA_V12P0_PWRGD is driven high by the [[ANA]] (later [[HANA]]) as long as the [[Power Rails#V_12P0|V_12P0]] rail is within tolerance. | ANA_V12P0_PWRGD is driven high by the [[ANA]] (later [[HANA]]) as long as the [[Power Rails#V_12P0|V_12P0]] rail is within tolerance. If V_12P0 ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter [[Error Codes#EC_FATAL|EC_FATAL]] and the 0001 code to be displayed on the front panel. | ||
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VREG_CPU_PWRGD is driven high by the CPU power controller as long as the [[Power Rails#V_CPUCORE|V_CPUCORE]] rail is within tolerance. If V_CPUCORE ever drops out of tolerance, the signal is de-asserted, the SMC | VREG_CPU_PWRGD is driven high by the CPU power controller as long as the [[Power Rails#V_CPUCORE|V_CPUCORE]] rail is within tolerance. If V_CPUCORE ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter [[Error Codes#EC_FATAL|EC_FATAL]] and the 0002 code to be displayed on the front panel. | ||
=== 0003 === | === 0003 === | ||
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VREG_GPU_PWRGD is driven high by the GPU power controller as long as the [[Power Rails#V_GPUCORE|V_GPUCORE]] rail is within tolerance. If V_GPUCORE ever drops out of tolerance, the signal is de-asserted, the SMC enters [[Error Codes#EC_FATAL|EC_FATAL]] | VREG_GPU_PWRGD is driven high by the GPU power controller as long as the [[Power Rails#V_GPUCORE|V_GPUCORE]] rail is within tolerance. If V_GPUCORE ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter [[Error Codes#EC_FATAL|EC_FATAL]] and the 0003 code to be displayed on the front panel. | ||
=== 0010 === | |||
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! Hex !! Name !! Description !! Repair Guide | |||
|- | |||
| 0x04 || ERROR_NO_ANA || [[ANA]]/[[HANA]] is not responding to reads or writes || [[Repair Guides/0010|0010]] | |||
|} | |||
The [[SMC]] communicates with the [[ANA]]/[[HANA]] via the SMBus. If communication is lost, the SMC enters [[Error Codes#EC_FATAL|EC_FATAL]] and the 0010 code is displayed on the front panel. | |||
{{Debug and Repair}} | {{Debug and Repair}} | ||
Revision as of 16:48, 5 January 2023
SMC Errors
These errors are generated by the System Management Controller.
0001
ANA_V12P0_PWRGD is driven high by the ANA (later HANA) as long as the V_12P0 rail is within tolerance. If V_12P0 ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter EC_FATAL and the 0001 code to be displayed on the front panel.
| Hex | Name | Description | Repair Guide |
|---|---|---|---|
| 0x01 | ERROR_V_12P0 | ANA_V12P0_PWRGD negated unexpectedly | 0001 |
0002
| Hex | Name | Description | Repair Guide |
|---|---|---|---|
| 0x02 | ERROR_V_CPUCORE | VREG_CPU_PWRGD negated unexpectedly | 0002 |
VREG_CPU_PWRGD is driven high by the CPU power controller as long as the V_CPUCORE rail is within tolerance. If V_CPUCORE ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter EC_FATAL and the 0002 code to be displayed on the front panel.
0003
| Hex | Name | Description | Repair Guide |
|---|---|---|---|
| 0x03 | ERROR_V_GPUCORE | VREG_GPU_PWRGD negated unexpectedly | 0003 |
VREG_GPU_PWRGD is driven high by the GPU power controller as long as the V_GPUCORE rail is within tolerance. If V_GPUCORE ever drops out of tolerance, the signal is de-asserted, causing the SMC to enter EC_FATAL and the 0003 code to be displayed on the front panel.
0010
| Hex | Name | Description | Repair Guide |
|---|---|---|---|
| 0x04 | ERROR_NO_ANA | ANA/HANA is not responding to reads or writes | 0010 |
The SMC communicates with the ANA/HANA via the SMBus. If communication is lost, the SMC enters EC_FATAL and the 0010 code is displayed on the front panel.